It is very common in the semiconductor (SC) device and integrated circuit (IC) arts to place contacts to a semiconductor (SC) body or layer in close proximity to other device regions that often must remain substantially insulated from such contacts. A well known example is source and/or drain (S-D) contacts of field effect transistors (FETs). The S-D contacts are electrical conductors that provide Ohmic electrical connections to underlying source and/or drain regions of the FET. Such source and/or drain (S-D) contacts are generally desired to be laterally very close to but insulated from a gate conductor that overlies and is insulated from the portion of the semiconductor body or layer between the source and drain regions. When the gate conductor is appropriately biased with respect to the S-D contacts and the S-D regions, it creates a conductive channel extending between the S-D regions. It is this controllable conductive channel that gives rise to the desirable properties of such FETs and of the ICs made up of multiple interconnected FETs.
There is an ongoing need to provide ever denser and more complex SC devices and ICs. This is accomplished in part by reducing the dimensions and spacing of the various device regions. The spacing and alignment of the various device regions are generally determined lithographically, that is by using doping, deposition and/or etching masks. However, as dimensions of the various mask openings and the spacing of such openings become smaller and smaller, alignment tolerance, dimensional tolerance and other errors inherent in the photo-lithographic process become more and more significant and can adversely affect manufacturing yield and cost. Thus, there is an ongoing need to be able to provide contacts closely spaced to but insulated from other device regions or elements where the structure and process used to form such contacts are more tolerant of inherent errors in contact alignment, placement and/or size. This is especially important in connection with field effect transistors (FETs) but also applies to many other semiconductor devices and ICs where contacts must be placed in close proximity to but insulated from other electrical conductors or device regions. Accordingly, the present invention is not limited to FETs but applies generally to any types of semiconductor devices and ICs where such closely spaced contacts are needed.